PIC16F84A-04E/SS【PDF 24/81 页】IC MCU CMOS 4MHZ 1K FLASH 20SSOP

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PIC16F84A

DS35007B-page 28

2001 Microchip Technology Inc.

FIGURE 6-9:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD):

SLOW VDD RISE TIME

6.7

Time-out Sequence and

Power-down Status Bits (TO/PD)

On power-up (Figures 6-6 through 6-9), the time-out

sequence is as follows:

PWRT time-out is invoked after a POR has

expired.

Then, the OST is activated.

The total time-out will vary based on oscillator configu-

ration and PWRTE configuration bit status. For exam-

ple, in RC mode with the PWRT disabled, there will be

no time-out at all.

TABLE 6-5:

TIME-OUT IN VARIOUS

SITUATIONS

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then

bringing MCLR high, execution will begin immediately

(Figure 6-6). This is useful for testing purposes or to

synchronize more than one PIC16F84A device when

operating in parallel.

Table 6-6 shows the significance of the TO and PD bits.

Table 6-3 lists the RESET conditions for some special

registers, while Table 6-4 lists the RESET conditions

for all the registers.

TABLE 6-6:

STATUS BITS AND THEIR

SIGNIFICANCE

VDD

MCLR

When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD

has reached its final value. In this example, the chip will reset properly if, and only if, V1

≥ VDD min.

INTERNAL POR

TPWRT

TOST

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

Oscillator

Configuration

Power-up

Wake-up

from

SLEEP

PWRT

Enabled

PWRT

Disabled

XT, HS, LP

72 ms +

1024TOSC

72 ms

——

Condition

Power-on Reset

Illegal, TO is set on POR

Illegal, PD is set on POR

WDT Reset (during normal operation)

WDT Wake-up

MCLR during normal operation

MCLR during SLEEP or interrupt

wake-up from SLEEP

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